High-speed PCB design has been a central research focus in the fields of electronic circuit design and manufacturing. In the 5G era, this area has encountered unprecedented opportunities for development. However, designing a high-performance high-speed PCB is no simple task. It requires not only higher density and operating speed but also the assurance of signal integrity, which directly affects electrical performance, reliability, and system stability. This article will delve into the key factors influencing signal integrity in high-speed PCB and present concrete optimization strategies to enhance the overall performance and stability of electronic systems. Let’s get started!
High-Speed PCB and Signal Integrity
High-speed PCB are designed to support high-speed signal transmission and are widely used in fields requiring high-frequency signals and large data processing, such as 5G communications, computers, and high-performance electronic devices. In these applications, the signal transmission rate and bandwidth requirements are extremely high, increasing the complexity of high-speed PCB design. Signal integrity (SI) refers to all electrical characteristics issues caused by interconnects in high-speed circuits, focusing on how interconnects interact with the voltage and current waveforms of digital signals and how these interactions impact product performance.
The issues with signal integrity in high-speed PCB become more pronounced due to higher signal frequencies, steeper rising and falling edges, and increased bandwidth demands. These factors pose stricter requirements for impedance matching and signal integrity along the transmission path. Additionally, as signal transmission speeds increase, the sampling time window at the receiving end shrinks significantly. This means any interference caused by signal distortion, reflection, or delay can have a more substantial impact on data transmission reliability.
Optimizing Signal Reflection
Signal reflection in circuits arises from impedance discontinuities in the transmission line. Specifically, when signals travel along a wire and encounter impedance changes, reflections occur at these points. Such impedance discontinuities act like “obstacles” that reflect part of the signal back, disrupting normal transmission.
For example, if the impedance of region 0 is 𝑍0 and region 1 is 𝑍1, the reflection coefficient (𝜏) can be expressed as:
From the formula, it is evident that the greater the impedance discontinuity between adjacent regions, the higher the amplitude of the reflected signal.
If region 0 has an impedance of 50Ω and region 1 has 0Ω, the reflection coefficient would be:-1. For a 5V LVTTL signal, this would result in a reflected voltage of -5V. The superposition of the incident and reflected voltages would result in 0V, effectively simulating a short-circuit condition.
Since transmission line impedance mismatch is the root cause of signal reflection, the following methods are commonly used to minimize its impact on signal integrity in high-speed PCB:
1. Source-End Series Resistor
A source-end series resistor is a method of signal damping achieved by connecting a resistor 𝑅𝑐 near the signal source, as shown in the figure below. The value of the series resistor 𝑅𝑐 is typically small, commonly ranging between 22Ω and 33Ω, and should be selected based on the transmission line impedance and signal characteristics. This method works by limiting current to suppress ground bounce noise to some extent. However, adding a series resistor increases the 𝑅𝐶 time constant, potentially slowing the signal rise time. As a result, it is not suitable for scenarios demanding high signal integrity, such as high-speed clocks.
2. Voltage Divider Termination
Voltage divider termination (also known as Thevenin termination) achieves impedance matching by connecting a resistive voltage divider network at the end of the signal line. The network consists of a pull-up resistor 𝑅1 and a pull-down resistor 𝑅2. When the equivalent impedance of the divider 𝑅𝑑 (𝑅𝑑= (𝑅1×𝑅2)/(𝑅1+𝑅2)) equals the transmission line impedance 𝑍0, optimal impedance matching is achieved.
This method effectively reduces reflection noise while setting a static voltage level when no signal is present on the transmission line, making it particularly suitable for bus circuit designs. However, due to the constant DC current flow in the divider, it increases power consumption and may reduce the signal’s noise margin.
3. Optimizing Topology
In circuit design, signal routing is often represented using topology structures, which are broadly classified into point-to-point and multi-drop topologies.
- Point-to-Point Topology: This connects the signal source directly to a single load, offering advantages such as easier impedance control and significantly improved signal integrity. However, in complex circuits, the increased number of routing paths can make the design more challenging.
- Daisy-Chain Topology: This is commonly used in bus systems with multiple loads, where the signal is transmitted sequentially to each node. It saves routing space and enables unified impedance matching but may introduce signal delays or reflections as the number of nodes increases.
- Star Topology: In multi-load systems, this connects the signal source separately to each load for synchronous transmission. While this structure provides synchronization, it may suffer from insufficient driving capability in high-speed circuits, impacting overall performance.
To select the most suitable topology, the characteristics of signal transmission and circuit requirements must be considered. For critical signal routing, it is advisable to use professional software for signal integrity analysis, simulating parameters like impedance matching, reflections, and delays to optimize the topology design and enhance the PCB’s overall performance.
Optimizing Signal Crosstalk
Signal crosstalk primarily originates from electromagnetic induction. When dynamic signals are transmitted, a varying electromagnetic field is generated, which can couple into adjacent static wires and induce noise signals.
Below is an idealized illustration of crosstalk between wires. In the diagram, segment 𝑀𝑁 represents the dynamic wire where signals are transmitted from point 𝑀 to 𝑁, while segment 𝑂𝑃 represents the static wire. During signal transmission, noise signals may couple into 𝑂𝑃, further interfering with other circuits. When the signal on 𝑀𝑁 stabilizes and becomes a DC signal, the coupled noise on 𝑂𝑃 diminishes and eventually disappears. Thus, the key factor causing crosstalk is signal transitions. Faster and larger current changes induce stronger noise in the static wire.
Crosstalk significantly affects high-speed circuits and can lead to unintended signal triggering. If the amplitude of the coupled noise pulse exceeds the receiver’s threshold, uncontrolled triggering signals may disrupt circuit logic, causing system malfunctions.
Measures to Suppress Signal Crosstalk:
- Follow the “3W” rule in routing, ensuring the spacing between lines is at least three times the line width to reduce coupling.
- In multilayer board stack-up designs, minimize the height between the signal layer and the ground layer while maintaining impedance requirements.
- Use termination techniques to achieve impedance matching, effectively reducing reflections and mitigating crosstalk.
- Avoid long parallel routing to minimize coupling regions.
- Select lower-speed components when timing requirements allow, reducing the electromagnetic field transition rate.
- Prioritize routing sensitive signals on internal layers to reduce external coupling interference.
Validation Testing
A 10-layer PCB based on DDR4 memory, operating at a frequency of 2.4 GHz and a voltage of 1.2 V, was selected for simulation and optimization. The Cadence Sigrity PowerSI tool was used for impedance simulation analysis. First, the 10-layer PCB file was imported into PowerSI for impedance analysis. The data bus section of the DDR4 was chosen for demonstration, and the simulation results are shown below.
In the figure, different color shades represent varying impedance values; for instance, regions with an impedance range of 40–50Ω are displayed in blue, while those in the range of 120–130Ω are shown in yellow. Analysis of the left image reveals impedance discontinuities in the PCB traces before optimization, which could lead to signal reflection and related issues.
Subsequently, the previously mentioned optimization measures were applied to re-route the PCB, and the results of the optimized design were verified through another round of simulation, as shown in the right image. The simulation clearly demonstrates that the continuity of the trace impedance has been significantly improved after optimization, resulting in a notable enhancement in signal integrity compared to the pre-optimization design.
Ending
Signal reflection and crosstalk are major factors affecting PCB signal integrity. By analyzing their causes and proposing effective solutions, we applied these measures to a high-speed PCB design. Simulation tools were used to validate signal integrity improvements. The results demonstrate that these measures significantly enhance signal quality, ensuring system stability in high-speed PCB.
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