In the trend of electronic miniaturization, integrated circuits are an essential component, and closely intertwined with integrated circuits is the field of packaging technology. The evolution of technologies such as BGA and CSP designs has undoubtedly enhanced reliability, but it has also compelled engineers to delve into the realm of high-density interconnects. Engineers are now required to consider HDI PCB stack-up designs to accommodate these intricate, miniature pins. Although designing boards with a higher number of layers can incur higher costs, they provide benefits such as high-frequency transmission capabilities and improved signal integrity. Therefore, it’s crucial to pay attention to your stack-up before commencing the layout process.
What is HDI PCB Stackup?
HDI PCB is typically defined as a board with a pin density ranging from 120 to 160 pins per square inch. It achieves high performance by employing various high-quality materials and features. The stack-up in design and manufacturing involves arranging different levels of the circuit board. This process involves the use of various types of vias and specific stack-up layers, including:
- Microvia: This has a smaller aspect ratio and does not penetrate the entire core material.
- Blind via: This via is visible on only one side of the board and does not traverse the entire PCB.
- Buried via: This via penetrates the internal layers of the board but is not visible from either side.
- Stacked via: Usually comprised of multiple microvias, it is used to connect different layers of the PCB.
HDI PCB Stack-Up Variation
As per the IPC (Printed Circuit Association) IPC-2315 standard, HDI’s stacking structure can be divided into Types I, II, III, IV, V, or Vi. This categorization employs the i+N+i notation, where “i” signifies the sequential stacking order of HDI layers on both sides of the “N” core layer. Common classifications include 1+N+1 and 2+N+2 stack-ups. However, depending on the specific application, a greater number of layers might be necessary.
The assembly of HDI PCB stack-ups follows a sequential lamination process. This involves etching copper traces and circuitry onto the inner layers, followed by stacking the layers together using prepreg material and heat compression. The sequential lamination process is carried out layer by layer, assembling them individually. After etching copper traces on the inner layers to establish electrical connections, the layers are stacked with prepreg material interposed between them. Heat is then applied to compress the HDI layers. Throughout the stack-up process, each layer within the circuit board undergoes metallization processes to enhance mechanical stability and durability, preventing cracks during operation.
Type I Stack-Up
Type I laminates employs a core structure with at least a single layer of microvias on one side. These stack-ups can include PTH vias and blind vias, but they exclude buried vias. However, Type I HDI encounters two limitations: the aspect ratio of PTH and potential delamination of ultra-thin FR-4 dielectrics under high temperatures. Consequently, for extensive boards with high pin counts, Type I HDI stack-ups may not be significantly advantageous compared to other laminates. This is due to the need for larger PTH through-hole pads to accommodate more layers. Furthermore, utilizing a single microvia layer doesn’t yield noteworthy performance enhancements.
Type II Stack-Up
Type II stack-up involve microvias, blind and buried vias on the core layers, with at least a single layer of microvias on one or both sides. Manufacturers can stagger microvias and position them opposite to or stacked against buried vias. This stack-up configuration offers advantages in achieving heightened performance.
Type III Stack-Up
Type III stack-up is well-suited for multi-layer, densely packed PCBs, particularly those featuring large fine-pitch BGAs. While encountering similar limitations as Types I and II, the use of microvias within inner layers grants more layers for signal routing. Employing stacked vias enables increased routing densities, albeit with higher associated costs.
Estimating the Required Number of HDI Stack-Up Layers
Various stacking techniques exist, making it difficult to pinpoint an exact number of layers. When it comes to design, factors such as trace density, network count, and spatial occupation play pivotal roles. Now, let’s delve into the procedure for approximating the appropriate number of stacked layers:
For novel HDI stack design projects, TechSparks recommends considering past experience when estimating PCB trace width; however, direct application is cautioned against. Each project’s attributes may vary, leading to the potential omission of crucial factors if solely relying on historical knowledge. Numerous online trace width calculation tools are available, offering more specialized insights to effectively manage signal impedance and achieve the desired signal transmission performance.
Furthermore, in densely circuit boards, establishing an upper limit for trace width based on BGA spacing aids in maintaining adequate separation between traces, preventing signal crosstalk issues. Concurrently, this upper limit can be utilized to calculate and ascertain the necessary layer thickness.
Network Estimation for Each Layer
Upon establishing the required trace width, thickness, and differential pair trace spacing, it becomes possible to make a rough calculation of the number of networks per layer within the HDI layout region. This approach involves factoring in the estimated board size, achieved by multiplying the approximate count of BGA breakout channels per unit area by the total board area, resulting in an estimated count of networks per layer.
The essence of this technique centers around area estimation, enhancing the comprehension of network distribution across each layer. By incorporating considerations of differential pair trace spacing and board dimensions, a more precise assessment of network density for each layer can be made. The outcomes of this method offer an informed approximation of the layer count for an HDI PCB.
After determining the network count necessary for each layer, you can easily divide the total network count by that figure to derive the required layer count. It’s important to note that this calculation method specifically pertains to signal layers, excluding the total layer count. Subsequently, by introducing power and ground planes into the HDI PCB’s layer stack, you establish an initial configuration for the layer count.
This calculation approach is grounded in the analysis of signal net quantities, offering a means to extrapolate the needed layer count for an HDI PCB. However, practical design adjustments may arise due to the inclusion of power and ground planes. This stage furnishes a valuable starting point for the design journey, yet it warrants subsequent fine-tuning in accordance with distinct requisites and engineering considerations.
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