Complementary Field-Effect Transistor (CFET)

As transistors continue to shrink, chip performance has witnessed a qualitative leap. However, this progress has brought forth challenges such as quantum effects and thermal issues. In response to these challenges, scientists have upgraded the traditional planar structure to three-dimensional structures, introducing FinFET and GAAFET. Yet, as transistor sizes approach the 2nm era, FinFET and GAAFET are gradually revealing limitations in coping with these challenges. Hence, a new technology has emerged to address these issues – Complementary Field-Effect Transistor (CFET), considered a key element for processes below 1nm. What revolutionary changes does the introduction of CFET transistor structures bring to the electronics industry?

CPU transistor art drawing

What is CFET Transistor and Its Purpose

The design of planar transistors allows for an increase in transistor density on chips by proportionally reducing transistor size. However, when the size shrinks to 28 nanometers, the short-channel effect becomes more prominent, leading to the development of FinFET and GAAFET.

  • FinFET: A three-dimensional transistor structure where the gate surrounds a thin fin-shaped channel.
  • GAAFET: Further innovation involves the gate completely surrounding the channel, not limited to the bottom and sides.

FinFET and GAA

The so-called CFET is, in fact, an improvement based on the Nanosheet structure. Nanosheet is a variant of GAAFET, where the transistor’s channel consists of multiple thin-sheet materials, and the gate surrounds these sheets. In CFET technology, a p-type Nanosheet FET is vertically stacked on top of an n-type Nanosheet FET, forming a three-dimensional transistor.

CFET transistor structure

According to the latest information from TSMC (Taiwan Semiconductor Manufacturing Company), adopting CFET vertical stacking structure can reduce chip area by 50% compared to GAAFET Nanosheet.

Latest Developments in CFET Transistor Technology


TSMC has reported initial success in the development of CFET transistors. They have achieved a gate pitch of 48nm, and laboratory testing for efficiency and performance is currently underway.

During the IEEE International Electron Devices Meeting, TSMC introduced the unique design and manufacturing methods of CFET transistors aimed at addressing leakage issues and improving power efficiency. A key technology involves introducing a dielectric layer between the top and bottom devices, effectively isolating them.

To further increase chip integration, TSMC has employed advanced isolation methods in the CFET transistor process, building the isolation layer before releasing the silicon nanowires. Specific etching techniques have successfully removed silicon-germanium material from the nanosheets, while utilizing germanium-enriched material for faster etching.


In the research of CFET transistors, Samsung has shown remarkable progress, referring to this structure as 3DSFET. They have achieved gate pitches of 45/48nm. In terms of technological innovation, Samsung has successfully achieved effective electrical isolation of source and drain for stacked pFET and nFET devices. To achieve this innovation, they have adopted a novel dry etching method, replacing traditional wet chemical etching steps, significantly improving the yield of CFET transistors in the chip.


Intel is one of the earliest companies to showcase research results in CFET transistor technology. By combining the CFET transistor structure with backside power supply technology, they have successfully achieved a gate pitch of 60nm. Intel emphasizes the uniqueness of this innovation by combining PMOS and NMOS together, providing complementary switch speeds and drive capabilities, significantly enhancing overall performance.

Challenges of CFET Transistor

After understanding the benefits of the CFET structure, many envision a transformed world post its introduction. However, industry experts predict that achieving commercialization of CFET transistors will take at least another 10 years. This is due to the difficulty in completing stacking in manufacturing and the cost issues associated with new technology.

Currently, the process path for CFET involves a multi-layer structure of epitaxial growth of PFET and NFET devices, followed by manufacturing FET on each epitaxial layer. This significantly increases the complexity of device manufacturing, as most of the effective process methods used in FinFET and GAAFET are no longer applicable. For example, in the FET source-drain module, ion implantation processes cannot be used for doping the source-drain; instead, doping elements need to be introduced near the source-drain through on-line epitaxy, achieved through a specific etching technique. These changes require the development of an entirely new process, gradually matured, making it a time-consuming project.

In the new process of CFET, one of the biggest challenges is the thermal annealing of multilayer stacking. Semiconductor materials may have structural defects for various reasons during crystal growth and manufacturing processes, and thermal annealing can repair the material, improving electrical conductivity and electrical performance. However, compared to non-stacking structures, stacking structures require thermal annealing for each layer, and the stability of metal connections at high temperatures is also a concern. This makes the use of laser local annealing necessary, but this not only increases the difficulty of the process but also raises the overall cost of chip manufacturing.

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