How to Avoid Parasitic Effects in High-Speed PCB Via Design

The significance of PCB vias is self-evident, as they serve multiple functions within a circuit, including electrical connections, mechanical support, and thermal management. In high-speed circuitry, the roles of these vias are further amplified. Designers often opt for multi-layered circuit structures and incorporate advanced techniques like blind and buried vias to enhance circuit performance. However, while these advanced vias bring benefits, they also come with some hidden impacts, one of which is parasitic effects.

Parasitic effects refer to unexpected electromagnetic phenomena within electronic components or circuits that may interfere with or affect circuit performance. This issue can be addressed through optimization of high-speed PCB via designs. Here, we will explore optimization measures using formulas for parasitic capacitance and parasitic inductance:

PCB thickness and aperture relationship diagram

The formula for parasitic capacitance is expressed as: C = 1.41εhD^2 / (D1 – D2)


  • ε: Dielectric constant, influenced by the PCB substrate;
  • h: Board thickness;
  • D1: Clearance distance from the via edge to the copper layer;
  • D2: Outer diameter of the via;

Based on the formula, the following conclusions can be drawn:

  • When the substrate material and board thickness remain constant, parasitic capacitance is inversely proportional to D1 and directly proportional to D2.
  • When board thickness, D1, and D2 all remain constant, the dielectric constant is directly proportional to parasitic capacitance.
  • When the dielectric constant, D1, and D2 all remain constant, board thickness is directly proportional to parasitic capacitance.

The formula for parasitic inductance is expressed as: L = 5.08h[ln(4h/d) + 1]


  • d: Inner diameter of the via

Based on the formula, the following conclusions can be drawn:

  • Board thickness is directly proportional to parasitic inductance.
  • Inner diameter of the via is inversely proportional to parasitic inductance.

While the impact of parasitic effects in conventional circuits can often be negligible, it becomes significant in high-speed circuits. As analyzed above, even simple vias can burden the circuit. So, how can these effects be mitigated? TechSparks provides several optimization measures for high-speed PCB via design:

  • For general vias, recommend dimensions of 10/20/36 (drill hole/solder pad/POWER isolation area).
  • Use larger vias to reduce power or ground impedance.
  • Increase the size of the POWER isolation area.
  • Avoid multiple vias for high-speed signal lines.
  • Control board thickness by using thinner PCBs to reduce parasitic parameters.

These measures are theoretical in nature, and practical circuit design considerations must also account for cost, signal quality, and the manufacturer’s production capabilities. However, one principle remains unchanged: high-speed PCB vias can induce parasitic effects. Therefore, minimizing the number of vias while ensuring design integrity and limiting high-speed signal lines to no more than three vias is advisable.

Related Articles:

Impact of Via Stub on High-Speed PCB Signal Transmission

High Speed PCB Design Practical Tutorial

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